What We Do
RADLogic’s many years of experience in IC design means that it is able to provide a low risk, made to order design to suit each of our customers’ unique requirements.
Whether our customer is a large corporation or a small start-up, we aim to work in partnership with them to turn their innovations into silicon. Customer confidentiality is often important to our customers and is of paramount importance to us. In combination with our competitive pricing and quick response time this has led to many long term relationships with customers.
RADLogic is happy to be involved in any or all of your Integrated Circuit Development tasks, depending upon your needs. We have experience ranging from analysing algorithms and developing and specifying chip architectures through to implementation all the way down to mask layout and verification of databases to be submitted to a foundry for manufacture.
Common activities include:
- Project Planning, Feasibility Studies and Project Management
- Requirements Analysis
- Feasibility Analysis
- Effort Estimation Project Planning and and Scheduling
- Product Specification
- Project Tracking and Reporting
- Digital and Full Chip Tasks
- High Level modelling in System Verilog, C, Python or other high level languages.
- Modelling using hardware description languages such as Verilog and VHDL.
- Digital Logic Simulation
- Logic Synthesis and Partitioning.
- Full chip Floorplanning
- Standard cell and Macro Placement and Routing.
- Clock Insertion
- Scan Insertion
- Timing Closure
- Power Analysis
- Extraction of SPEF or SDF for futher timing analysis
- Post-layout simulations
- Full chip Physical Verification (DRC & LVS)
- Foundry Interface
- Packaging Interface
- Test-House Interface
- Test Vector Development
- Design of dedicated test hardware
- Evaluation test
- Analog Design Tasks
- Signal flow planning
- Circuit Design-
- Schematic Capture
- Analog Circuit Simulation (Spice)
- Manual and/or generator based mask layout
- RF layout, common-centroid layout, guard rings…
- Incorporation of thrid-party IP
- Analog floorplanning and routing
- Post layout simulations uncluding extracted parastics
- Physical Verification (DRC & LVS, ERC).
As well as designing complete chips, RADLogic also develops intellectual property blocks for other designers to use within their own designs. See our product listings for some of the IP blocks we have developed. We can provide whatever data you require for your design environment, but typically this will include:
- Digital IP Deliverables (soft macros)
- Synthesisable HDL (Verilog or VHDL)
- Synthesis Guidelines
- Design Documentation
- Analog IP Deliverables (hard macros)
- Design Specification and Design Documentation
- Analog schematics (PDF format)
- Liberty Timing File
- LEF Model for P&R
- GDSII Layout for the target technology
- Corresponding Spice netlist for LVS verification.
RADLogic has experienced digital designers who can help to develop HDL code and implement the design in an FPGA to meet your requirements.
We often implement FPGA based circuits as hardware emulators or as test/evaluation platforms for chips we have designed, or as indepenent systems.
RADLogic is also competent with designing and programming microcontroller-based products.
We use Altium Designer for PCB design work, often to design test boards for evaluation of our chips and also to design systems using off-the-shelf hardware from third party suppliers.
In addition to RADLogic’s experience with RFID devices, we also have experience in developing Bluetooth controlled equipment controlled by smartphones or tablets using Apps we have developed in-house. An example is a Medical device controlling a customised Radio Frequency Ablation System for the treatment of tumors.
This technology has potential to be used in many other commercial and industrial applications, lowering system and development costs by taking advantage of existing user interface, control and communication mechanisms.
Our primary focus is designing products for our customers (and they retain ownership of their designs). However, over the years we have developed a number of in-house designs that we can license to customers. Examples include our digital protocol engine for the EPC Gen 2 Class 1 protocol (V1.2) and our corresponding UHF Analog front end. For more information about our products, please see our Products listing.
RADLogic has experience with a wide range of technologies and are independent of any particular wafer foundry. We are happy to work with the foundry and technology of your choice or can help you chose a suitable technology for your application.
We predominantly work with CMOS technologies at technology nodes of 55nm, 130nm or 180nm and have experience with analog features such as high voltage devices, double poly, MIM and Metal finger capacitors, bipolar devices, native devices, triple well, LDMOS, DMOS, high valued resistors, EEPROM, OTP, FRAM, LCOS, optical devices, and more.
RADLogic has experience with many of the leading design tool suites. We hire time based-licenses for Synopsys and Cadence tools on an as needed basis (e.g., as per customer requirements), have licenses for key Mentor Graphics tools, as well as a number of PC based tools, and we have also developed some of our own in-house design tools. We have experience with the following tool suites:
• Synopsys HSPICE
• Synopsys Custom Designer
• Synopsys Laker Level 3
• Synopsys ICC
• Cadence Spectre
• Cadence Virtuoso
• Cadence Encounter
• Cadence Encounter Test
• Cadence PVS, Assura
• Mentor Graphics Calibre
• Mentor Graphics Modelsim
• Mentor Graphics GDT Suite
• Mentor Graphics Autocells
• Aldec Riviera
• Silvaco SmartSpice
• Altium Designer, Protel, Altera Quartus, LTSpice, Klayout, and many other PC based Design Tools